processors · d-matrix
Digital in-memory-compute inference card holding weights in SRAM rather than HBM, trading capacity for very high effective bandwidth on batch-served LLMs.
| Method | vendor-published-specification |
|---|
| Publisher | d-matrix |
|---|---|
| Origin | United States |
| Licence | vendor |
Registry record as of 2026-08-12. Identity, licence and parameter count are properties of a release and do not move; tier can, and the verify link above re-checks it against the live registry rather than this page.