processors · google
4th-gen TPU with optically-reconfigurable 3D-torus interconnect. 275 TFLOPs BF16 per chip; backbone of large-scale Google training.
| Weight file SHA-256 | 476e7095930e84fb8b9f181002db7a49434f10d2eb1764c4d3066f504debe05f |
|---|
| Publisher | |
|---|---|
| Origin | United States |
| Licence | vendor |
| Pulls recorded here | 14,801 |
Registry record as of 2026-06-06. Identity, licence and parameter count are properties of a release and do not move; tier can, and the verify link above re-checks it against the live registry rather than this page.