processors · sambanova
Reconfigurable dataflow unit with a three-tier memory hierarchy (on-chip SRAM, HBM, and large DDR), aimed at serving many large models from one node.
| Method | vendor-published-specification |
|---|
| Publisher | sambanova |
|---|---|
| Origin | United States |
| Licence | vendor |
Registry record as of 2026-08-12. Identity, licence and parameter count are properties of a release and do not move; tier can, and the verify link above re-checks it against the live registry rather than this page.